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Product Description
Sirenza Microdevices' SGA-8343 is a high performance Silicon Germanium Heterostructure Bipolar Transistor (SiGe HBT) designed for operation from DC to 6 GHz. The SGA-8343 is optimized for 3V operation but can be biased at 2V for low-voltage battery operated systems. The device provides high gain, low NF, and excellent linearity at a low cost. It can be operated at very low bias currents in applications where high linearity is not required. The matte tin finish on Sirenza's lead-free package utilizes a post annealing process to mitigate tin whisker formation and is RoHS compliant per EU Directive 2002/95. This package is also manufactured with green molding compounds that contain no antimony trioxide nor halogenated fire retardants.
Typical Performance - 3V, 10mA
40 35 30 25 20 15 10 5 0 0 1 2 2 .4 2 .1 1 .8 1 .5 1 .2
Gmax Gain
SGA-8343 SGA-8343Z
Pb
RoHS Compliant & Green Package
Low Noise, High Gain SiGe HBT
Preliminary
Product Features
* Now Available in Lead Free, RoHS Compliant, & Green Packaging * DC-6 GHz Operation * 0.9 dB NFMIN @ 0.9 GHz * 24 dB Gmax @ 0.9 GHz * |GOPT|=0.10 @ 0.9 GHz * OIP3 = +28 dBm, P1dB = +9 dBm * Low Cost, High Performance, Versatility
Gain, Gmax (dB)
NFMIN
Applications
Analog and Digital Wireless Systems 3G, Cellular, PCS, RFID Fixed Wireless, Pager Systems Driver Stage for Low Power Applications * Oscillators * * * *
NFMIN (dB)
0 .9 0 .6 0 .3 0 6 7 8
3 4 5 Frequency (GHz)
Symbol
D evice C haracteristics
Test C onditions VCE=3V, ICQ=10mA, 25C (unless otherw ise noted)
Test Frequency
U nits
Min.
Typ.
Max.
GMAX
Maxi mum Avai lable Gai n
ZS=ZS*, ZL=ZL*
0.9 GHz 1.9 GHz 2.4 GHz 0.9 GHz 1.9 GHz 2.4 GHz 0.9 GHz 1.9 GHz 1.9 GHz 1.9 GHz 1.9 GHz
dB
23.9 19.3 17.7 0.94 1.10 1.18 21.0 22.0 1.40 15.5 25.8 7.5 120 16.5 27.8 9.0 180 6.0 200 4.0 50 300 23.0 1.75 17.5
NF S 21 NF Gai n OIP3 P 1dB hFE B V C EO Rth V CE ICE
Mi ni mum Noi se Fi gure Inserti on Gai n[1] Noi se Fi gure[2] Gai n[2] Output Thi rd Order Intercept Poi nt[2] Output 1dB C ompressi on Poi nt[2] D C C urrent Gai n C ollector-Emi tter Breakdown Voltage Thermal Resi stance Operati ng Voltage Operati ng C urrent
ZS=GammaOPT, ZL=ZL* ZS=ZL= 50 Ohms LNA Appli cati on C i rcui t Board LNA Appli cati on C i rcui t Board LNA Appli cati on C i rcui t Board LNA Appli cati on C i rcui t Board
dB dB dB dB dB m dB m
V juncti on-to-lead collector-emi tter collector-emi tter
o
5.7
C /W V mA
[1] 100% tested - Insertion gain tested using a 50 ohm contact board (no matching circuitry) during final production test. [2] Sample tested - Samples pulled from each wafer/package lot. Sample test specifications are based on statistical data from sample test measurements. The test fixture is an engineering application circuit board (parts are pressed down on the circuit board). The application circuit represents a trade-off between the optimal noise match and input return loss.
The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or omissions. Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. Sirenza Microdevices does not authorize or warrant any Sirenza Microdevices product for use in life-support devices and/or systems. Copyright 2003 Sirenza Microdevices, Inc. All worldwide rights reserved.
303 Technology Court, Broomfield, CO 80021
Phone: (800) SMI-MMIC
http://www.sirenza.com
1
EDS-101845 Rev F
SGA-8343 Low Noise SiGe HBT
Junction Temperature Calculation
MTTF is inversely proportional to the device junction temperature. For junction temperature and MTTF considerations the device operating conditions should also satisfy the following expression: PDC < (TJ - TL) / RTH where: PDC = ICE * VCE (W) TJ = Junction Temperature (C) TL = Lead Temperature (pin 2) (C) RTH = Thermal Resistance (C/W)
Absolute Maximum Ratings
Parameter Collector Current Base Current Collector - Emitter Voltage Collector - Base Voltage Emitter - Base Voltage RF Input Power Storage Temperature Range Power Dissipation Operating Junction Temperature Symbol ICE IB VCE VCB V EB PIN Tstor PDISS TJ Value 72 1 5 12 4.5 5 -40 to +150 350 +150 Unit mA mA V V V dB m C mW C
Biasing Details
The SGA-8343 should be biased through a dropping resistor or with active bias circuitry to prevent thermal runaway and combat Beta variation. For passive biasing it is recommended that the voltage drop be at least 20% of VCE. A voltage divider from collector-to-base is preferred over a simple series resistor. The effect of Beta variation can be minimized by bleeding ~10*IB through the shunt resistor.
Operation of this device beyond any one of these limits may cause permanent damage. For reliable continuous operation, the device voltage and current must not exceed the maximum operating values specified in the table on page 1.
Typical Performance - Engineering Application Circuits (See App Note AN-044)
Freq (GHz ) 0.90 1.575 1.90 2.40
[3]
Vs (V) 5.0 3.3 5.0 3.3
VCE (V) 3.0 2.7 3.0 2.7
ICQ (mA) 12 10 12 10
NF (dB) 1.25 1.25 1.4 1.6
Gain (dB) 18.2 15.7 16.5 14.4
P1dB OIP3[3] (dBm) (dBm) 9 6.8 9 9 27.3 26.5 27.8 27.5
S11 (dB) -16 -10 -9 -13
S 22 (dB) -18 -25 -24 -24
Comments series feedback see AN-061
POUT= 0 dBm per tone, 1MHz tone spacing
Refer to the application note for additional RF data, PCB layouts, BOMs, biasing instructions, and other key issues to be considered. For the latest application note please visit our site at www.sirenza.com.
Peak RF Performance Under Optimum Matching Conditions
Freq (GH z ) 0.90 1.90 2.40
[4] [5]
VCE (V) 2 3 2 3 2 3
ICQ (mA) 10 10 10 10 10 10
N FMIN [4] (dB ) 0.90 0.94 1.05 1.10 1.15 1.18
Gmax (dB ) 23.7 23.9 19.1 19.3 17.4 17.7
P1dB [5] (dB m) 10 13 10 13 10 13
OIP3 [6] (dB m) 25 29 25 29 25 29
ZSOPT E B ZLOPT C
ZS=OPT, ZL=ZL*, The input matching circuit losses have been de-emebedded. ZS=ZSOPT, ZL=ZLOPT, where ZSOPT and ZLOPT have been tuned for max P1dB (current allowed to drive-up with constant VCE) [6] ZS=ZSOPT, ZL=ZLOPT, where ZSOPT and ZLOPT have been tuned for max OIP3 Note: Optimum NF, P1dB, and OIP3 performance cannot be achieved simultaneously.
303 Technology Court, Broomfield, CO 80021
Phone: (800) SMI-MMIC
http://www.sirenza.com
EDS-101845 Rev F
2
SGA-8343 Low Noise SiGe HBT
Typical Performance - De-embedded S-Parameters
Gain vs Frequency (3V,10mA)
40 0 -5 -10
Isolation
Minimum Noise Figure (3V,10mA)
2.4 2 30 25 20
FMIN GAS
Gain, Gmax (dB)
35 30 25 20 15 10 5 0 0 1 2 3 4 5 6 7 8
Gain Gmax
Isolation (dB)
NFMIN (dB)
-15 -20 -25 -30 -35 -40
1.6 1.2 0.8 0.4 0 0 1 2 3 4 5 6 7
GAS (dB)
15 10 5 0
Frequency (GHz) S11,S22 vs Frequency (3V,10mA)
1.0 0.5 2.0 0.5
Frequency (GHz) OPT (3V,10mA)
1.0 2.0
8 GHz 6 GHz
0.2 5.0 0.2 5.0
4 GHz 1.9 GHz 3 GHz
0.0 0.2 0.5 1.0 2.0 5.0 0.0 inf 0.2
2.4 GHz 3 GHz 4 GHz S22
0.5
0.9 GHz
1.0 2.0 5.0 inf
2 GHz
0.2
5.0
0.2
5 GHz
5.0
1 GHz S11
0.5 2.0 0.5
6 GHz
2.0
1.0
1.0
Note: S-parameters are de-embedded to the device leads with ZS=ZL=50. The device was mounted on a 0.010" PCB with plated-thru holes close to pins 2 and 4. De-embedded s-parameters can be downloaded from our website (www.sirenza.com).
Typical Performance - Noise Parameters - 3V,10mA
Frequency (GH z ) 0.9 1.9 2.4 3 4 5 6 N FMIN[7] (dB ) 0.94 1.1 1.18 1.27 1.5 1.73 2.02 OPT Mag Ang 0.10 55 0.17 125 0.23 157 0.23 179 0.29 -150 0.42 -122 0.55 -110 rn ( ) 0.11 0.10 0.09 0.09 0.12 0.18 0.24 Gmax (dB ) 23.88 19.33 17.66 15.01 11.94 9.84 8.62
[7] ZS=OPT, ZL=ZL*, NFMIN is a noise parameter for which the input matching circuit losses have been de-emebedded. The noise parameters were measured using a Maury Microwave Automated Tuner System. The device was mounted on a 0.010" PCB with platedthru holes close to pins 2 and 4.
303 Technology Court, Broomfield, CO 80021
Phone: (800) SMI-MMIC
http://www.sirenza.com
EDS-101845 Rev F
3
SGA-8343 Low Noise SiGe HBT
Caution: ESD sensitive
Appropriate precautions in handling, packaging and testing devices must be observed.
Pin Description
Pin #
1 2 3 4
Part Number Ordering Information
Part N umber R eel Siz e 7" 7" D evices/R eel 3000 3000 SGA-8343 SGA-8343Z
Function
B a se Emitter Collector Emitter
Description
RF Input / Base Bias Connection to ground. Use multiple via holes to reduce emitter inductance. RF Output / Collector Bias Same as Pin 2
Part Symbolization The part will be symbolized with the "A83" or "A83Z" designator and a dot signifying pin 1 on the top surface of the package.
MARKING
4 3
4 3
Recommended PCB Layout
SOT-343 Package
A83
1 2
1
A83Z
2
Plated Thru Holes (0.020" DIA)
Ground Plane
Use multiple plated-through vias holes located close to the package pins to ensure a good RF ground connection to a continuous groundplane on the backside of the board.
D e e
Package Dimensions
L
HE
C L
A83
C L
E
SYMBOL E MIN 1.15 1.85 1.80 0.80 0.80 0.00 0.10 MAX 1.35 2.25 2.40 1.10 1.00 0.10 0.40
Q1 b1 C
D HE A A2 A1
b
NOTE: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONS ARE INCLUSIVE OF PLATING. 3. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH & METAL BURR. 4. ALL SPECIFICATIONS COMPLY TO EIAJ SC70. 5. DIE IS FACING UP FOR MOLD AND FACING DOWN FOR TRIM/FORM. ie :REVERSE TRIM/FORM. 6. PACKAGE SURFACE TO BE MIRROR FINISH.
Q1 e b b1 c L
0.65 BSC 0.25 0.55 0.10 0.10 0.40 0.70 0.18 0.30
A2
A A1
303 Technology Court, Broomfield, CO 80021
Phone: (800) SMI-MMIC
http://www.sirenza.com
EDS-101845 Rev F
4

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